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Hardware Description Languages / Beginner

Verilog Tutorial

A focused Verilog curriculum covering syntax, core language or platform semantics, data/control flow, tooling, and advanced features through atomic topic-specific lessons.

80 lessons~13.3 hoursvVerilog-2001 / SystemVerilog workspace_premium Certificate available
YOUR PROGRESS
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Course curriculum

MODULE 01
Modules & Nets
10 lessons
1module
10 min
2input output
10 min
3wire
10 min
4reg
10 min
5logic
10 min
6parameter
10 min
7localparam
10 min
8module instantiation
10 min
9named port mapping
10 min
10generate
10 min
MODULE 02
Combinational Logic
10 lessons
1assign
10 min
2always @*
10 min
3always_comb
10 min
4blocking assignment
10 min
5ternary operator
10 min
6case
10 min
7casez
10 min
8casex caveat
10 min
9concatenation
10 min
10replication
10 min
MODULE 03
Sequential Logic
10 lessons
1always posedge
10 min
2nonblocking assignment
10 min
3always_ff
10 min
4synchronous reset
10 min
5asynchronous reset
10 min
6clock enable
10 min
7counter
10 min
8shift register
10 min
9edge detector
10 min
10register pipeline
10 min
MODULE 04
Data & Operators
10 lessons
1bit vector
10 min
2signed value
10 min
3part select
10 min
4indexed part select
10 min
5arithmetic operators
10 min
6logical operators
10 min
7bitwise operators
10 min
8reduction operators
10 min
9shift operators
10 min
10comparison operators
10 min
MODULE 05
Procedural Control
10 lessons
1if else
10 min
2for loop
10 min
3while loop
10 min
4repeat
10 min
5forever
10 min
6break
10 min
7continue
10 min
8function
10 min
9task
10 min
10automatic lifetime
10 min
MODULE 06
Finite State Machines
10 lessons
1state parameter
10 min
2enum state
10 min
3state register
10 min
4next-state combinational
10 min
5Moore FSM
10 min
6Mealy FSM
10 min
7default state recovery
10 min
8one-hot state
10 min
9output register
10 min
10transition condition
10 min
MODULE 07
Testbenches
10 lessons
1initial block
10 min
2delay control
10 min
3clock generation
10 min
4$display
10 min
5$monitor
10 min
6$finish
10 min
7test vector loop
10 min
8task stimulus
10 min
9$readmemh
10 min
10assert property
10 min
MODULE 08
Advanced RTL
10 lessons
1interface
10 min
2modport
10 min
3struct packed
10 min
4union packed
10 min
5typedef
10 min
6package import
10 min
7generate if
10 min
8generate for
10 min
9parameterized module
10 min
10signed arithmetic
10 min
Certificate Included

Verilog Certificate

Earn this credential in either of two ways: complete 100% of the course, or take the master exam directly and score 85% or higher. You do not need to finish the course before attempting the exam.

Course completion path
Finish every published lesson → completion certificate is issued automatically.
Mastery exam path
15 MCQs · 100 marks · 30 minutes · 85% pass · 4 attempts.
Fresh questions each attemptNo backtrackingPublic verificationAdd to LinkedIn
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